Known own from U.S. Pat. Nos. 5,218,569 and 5,394,362 are multi-level non-volatile memories of this type. The construction of a FLASH EEPROM multi-level memory is also described in an article TA 7.7, "A Multilevel Cell 32Mb Flash Memory", ISSCC95 Conference, Feb. 16, 1995.
These publications also address and solve the problem of programming or writing by a cyclical repetition of program pulses and verification steps; specifically, a cell to be written into is applied, between its gate and source terminals, a voltage write pulse from a row decoding circuit which is power ed by a supply circuit. The cell is then read from to verify the level of its threshold voltage and decide on whether a new pulse is to be applied thereto or the programming brought to an end.
The above article postulates a four-level program and a distribution of the threshold voltages of approximately 500 mV for each level. This involves a spacing of about 500 mV between levels, for a supply voltage of about 3.3 V to the integrated electronic storage device.
If the supply voltage were lower, as is in the wish of so many manufacturers of electronic apparatus for telecommunications applications, for example, such values would have to be reduced, and be reduced still further as the number of the levels increases.
The provision of distributions so narrow and levels so close together requires extended programming times, because the number of the program cycles has to be increased, as well as highly sophisticated and complex read circuits.
This invention is based on the observation that, when a set of non-volatile memory cells having a given distribution of threshold voltages are subjected to the same electrical "treatment", the distribution remains near-constant and shifts in voltage by an amount not determinable with any great accuracy.
This invention proposes, therefore, of arranging for the write operations to be electrically identical for all the cells; this being accomplished by so regulating the write voltage as to make it independent of at least the supply voltage.
To avoid read errors due to shifting inaccuracy, it would be of advantage if the levels could be well spaced apart; this being obtained by generating a high write voltage internally with respect to the supply voltage.
With the levels well spaced apart, the write operation is less critical, and can be carried out advantageously with a single pulse of properly regulated width and duration.